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| SM5170AV NIPPON PRECISION CIRCUITS INC. PLL Synthesizer IC OVERVIEW The SM5170AV is a PLL synthesizer IC developed for application in pagers. It incorporates independently-controlled reference frequency and FIN input frequency dividers, and operates from a low-voltage supply to realize low power dissipation. It features a charge pump that operates at 3 V, making possible a wide range of VCO designs. FEATURES s s Supply voltages * VDD1 = 0.95 to 1.2 V (prescaler, counters) * VDD2 = 2.0 to 3.3 V (charge pump) FIN input frequency * fFIN = 300 MHz (VDD1 = 0.95 V) * fFIN = 330 MHz (VDD1 = 1.0 V) s s s s s Reference frequency * fXIN = 25 MHz (VDD1 = 0.95 V) 20 to 262140 reference frequency divider ratio range (with 1/4 prescaler built-in) 1056 to 131071 FIN input frequency divider ratio range -10 to 60 C operating temperature range 16-pin VSOP PINOUT (Top view) XIN XOUT VDD2 DB DO VSS FIN VDD1 1 16 TEST NC OPR LE DATA CLK LD 5170AV 8 9 NC ORDERING INFORMATION D e vice S M 5 1 7 0 AV P ackag e 16-pin V S O P NIPPON PRECISION CIRCUITS--1 SM5170AV PACKAGE DIMENSIONS Unit: mm 16-pin VSOP 4.4 0.2 6.4 0.2 0.10 0.05 5.1 0.2 1.15 0.1 0.275typ 0 0.15 - + 0..10 05 0 10 0.65 0.10 + 0.10 0.22- 0.05 0.12 M 0.5 0.2 BLOCK DIAGRAM VDD1 AREA(1V) XIN XOUT 1/4 Prescaler 16Bit R-Counter Boost Signal Generator DB VDD2 AREA(3V) CLK DATA LE Latch Selector 16Bit R-Latch 22Bit Shift Register Level Shifter Phase Detector Charge Pump DO 17Bit N-Latch OPR VDD1 AREA(1V) 5Bit Swallow Counter Lock Detector LD FIN Dual Modulus Prescaler 12Bit Main Counter NIPPON PRECISION CIRCUITS--2 SM5170AV PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XIN XOUT VDD2 DB DO VSS FIN VDD1 NC LD CLK D ATA LE OPR NC TEST I/O I O - O O - I - - O I I I I - I Supply 1V 1V 3V 3V 3V - 1V 1V - 1V 3V 3V 3V 3V - 1V Description Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can be connected to XIN. The clock is output on XOUT. Feedback resistor built-in for AC-coupled inputs. Phase comparator, charge pump and booster signal 3 V supply Booster signal output for faster locking Phase comparator output pin. Built-in charge pump and tristate output means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter. Ground pin FIN input frequency divider input pin. Feedback resistor built-in for AC-coupled inputs. Reference frequency and FIN input frequency prescaler and counter 1 V supply No connection Unlock signal output pin. (Unlocked when LOW). The function of LD can be turned OFF using the LD input control bit (LD should be tied LOW when not used). Control data clock input pin Control data input pin Control data latch enable signal input pin Pow er-save control pin. Start when HIGH, standby mode when LOW . No connection Test pin. Pull-down resistor built-in. Leave open or connect to ground for normal operation. SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V P arameter Supply voltage Symbol VDD1 VDD2 Input voltage range Storage temperature range Pow er dissipation V IN1 V IN2 T stg PD VDD1 VDD2 FIN, XIN, T E S T OPR, CLK, DATA, LE Condition Rating -0.3 to 2.0 -0.3 to 4.6 V S S - 0.3 to V D D 1 + 0.3 V S S - 0.3 to V D D 2 + 0.3 -40 to 125 150 Unit V V V V C mW Recommended Operating Conditions VSS = 0 V P arameter Supply voltage Operating temperature range Symbol VDD1 VDD2 T opr VDD1 VDD2 Condition Rating 0.95 to 1.2 2.0 to 3.3 -10 to 60 Unit V V C NIPPON PRECISION CIRCUITS--3 SM5170AV Electrical Characteristics VSS = 0 V, VDD1 = 0.95 to 1.2 V, VDD2 = 2.0 to 3.3 V, Ta = -10 to 60 C P arameter VDD1 operating current consumption VDD2 operating current consumption VDD1 standby current VDD2 standby current FIN maximum operating input frequency XIN maximum operating input frequency FIN minimum operating input frequency XIN minimum operating input frequency FIN input amplitude XIN input amplitude OPR, CLK, DATA, LE LOW -level input voltage OPR, CLK, DATA, LE HIGH-level input voltage FIN LOW -level input current XIN LOW -level input current FIN HIGH-level input current XIN HIGH-level input current D B L OW -level output voltage DB HIGH-level output voltage D O L OW -level output current DO HIGH-level output current D O , DB tristate output high-impedance leakage current D ATA CLK setup time CLK LE setup time Hold time Symbol ID D 1 ID D 2 Ist1 Ist2 fm a x 1 fm a x 2 fmin1 fmin2 V FIN1 V FIN2 V XIN V IL V IH IIL1 IIL2 IIH1 IIH2 VDOL VDOH ID O L ID O H IO Z L IO Z H tS U 1 tS U 2 tH See the timing diagra m s . V IL = 0 V V IH = V D D 1 Note 5. Note 6. Note 7. Note 8. VOL = 0 V VOH = VDD2 VDD2 - 0.5 1.0 1.0 - - 2 2 2 - - - - - - - - - 100 100 - - - Note 1. Note 2. Note 3. Note 4. 300 mVp-p sine w ave V D D 1 = 0.95 to 1.2 V V D D 1 = 1.0 to 1.2 V Condition Rating min - - - - 300 330 25 - - 0.3 0.3 0.3 - VDD2 - 0.3 - - - - typ 1.1 0.003 0.7 0.01 - - - - - - - - - - - - - - max 1.9 - - 10.0 - - - 40 9 - - - 0.3 - 60 10 60 10 0.5 Vp-p Vp-p V V A A A A V V mA mA nA nA s s s Unit mA A MHz MHz MHz MHz 300 mVp-p sine wave (external input) 300 mVp-p sine wave 300 mVp-p sine wave (external input) fFIN = 300 MHz, AC coupling fFIN = 330 MHz, V D D 1 = 1.0 to 1.2 V, A C coupling fX I N = 25 MHz, AC coupling (external input) 1. V D D 1 = 1.0 to 1.05V, V D D 2 = 2.7 to 3.3 V, fFIN = 310 MHz (300 mVp-p sine wave), fX I N = 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator frequency, OPR = HIGH, no output load, typ condition : V D D 1 = 1.0 V 2. V D D 1 = 0.95 to 1.2 V, V D D 2 = 2.7 to 3.3 V, fFIN = 310 MHz (300 mVp-p sine wave), fX I N = 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator frequency, OPR = HIGH, no output load, typ condition : V D D 2 = 3.0 V 3. V D D 1 = 1.0 V, V D D 2 = 3.0 V, OPR = LOW , no input/output load (i.e. CLK = DATA = LE = 0 V) 4. V D D 1 = 0 V, V D D 2 = 2.7 to 3.3 V, OPR = LOW , no input/output load (i.e. CLK = DATA = LE = 0 V), typ condition : V D D 2 = 3.0 V 5. DB output is derived from the V D D 2 supply. DB-pin condition select bit = (00001) 2 , V D D 2 = 2.7 to 3.3 V, no load 6. DB output is derived from the V D D 2 supply. DB-pin condition select bit = (11111) 2 , V D D 2 = 2.7 to 3.3 V, no load 7. DO output is derived from the V D D 2 supply. V D D 2 = 2.7 to 3.3 V, V O L = 0.4 V 8. DO output is derived from the V D D 2 supply. V D D 2 = 2.7 to 3.3 V, V O H = V D D 2 - 0.4 V DATA, CLK, and LE timing VIH VIH DATA CLK LE tSU1 VIH tH tSU2 VIH NIPPON PRECISION CIRCUITS--4 SM5170AV FUNCTIONAL DESCRIPTION Frequency Divider Data The input data should be specified keeping in mind the VDD2 supply. The data is input using CLK, DATA and LE pins into the shift register and latch which operate from the VDD2 supply. The VDD1 supply level, however, is not needed and can be ON or OFF. The control data input uses a 3-line 24-bit serial interface comprising the clock (CLK), data input (DATA) and latch enable (LE). The data is input with the MSB first. The last two bits (23rd + 24th) are used as the latch select control bits. Data is written to the shift register on the rising edge of the clock signal. Accordingly, the data should change state on the falling edge of the clock signal. Data is transferred from the shift register to the latch when the latch enable (LE) signal goes HIGH. Accordingly, the latch enable signal should be held LOW while data is being written to the shift register. The clock and data input signals are both ignored when the latch enable signal goes HIGH. Also, the CLK, DATA and LE inputs should be tied LOW when not setting data. CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DATA MSB LE Control bits 24 LSB Figure 1. Frequency divider data format Input Data Description Latch select MSB 1 LSB 24 DATA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Control bits Figure 2. Latch select data format The last two data bits determine the status of the shift register data latch. Bit 23 0 0 Bit 24 0 1 Latch S w allow counter and main counter frequency divider ratio latch select Reference frequency counter divider ratio data and LD output latch select FIN input frequency Divider (N-counter) Structure The FIN input frequency divider generates a comparator frequency signal (FV), which is input to the phase comparator, by dividing the VCO signal input on pin FIN. Frequency settings Prescaler Swallow counter Main counter FIN input frequency divider ratio The phase comparator is comprised of dual modulus prescalers, a 5-bit swallow counter and a 12-bit main counter. P and P + 1 S M N = (P + 1) x S + P x (M - S) N = P x M + S (where M > S) P = 32, P + 1 = 33 S = 0 to 31 M = 32 to 4095 N = 1056 to 131071 NIPPON PRECISION CIRCUITS--5 Prescaler Swallow counter Main counter FIN input frequency divider ratio range Counter set ranges SM5170AV Swallow counter and main counter data The swallow counter and main counter which determine the FIN input frequency divider ratio are set by MSB 1 2 11 2 2 10 3 29 4 28 5 27 6 26 7 25 8 24 9 23 10 22 11 21 12 20 13 24 bits 1 to 12 and bits 13 to 17, respectively. The voltage signal output on pin DB is set by bits 18 to 22. 14 23 15 22 16 21 17 20 18 24 19 23 20 22 21 21 22 20 23 LSB 24 Main Counter (12bit : 32 to 4095) Control bits Swallow Counter (5bit : 0 to 31) DBpin Condition Select bits Figure 3. Swallow counter and main counter frequency divider data format FIN input frequency divider example If the VCO output is (fVCO), the output frequency (fLO) is 251.3 MHz, and the channel bandwidth (fCH: Phase comparator frequency (fR)) is 25 kHz, then the FIN input frequency divider ratio N is given by: f LO f VCO 251.3 N = --------- = ------------- = ------------ = 10052 f CH fN 0.025 = 32 x 314 + 4 Therefore, the swallow counter count is 4 (00100)2 and the main frequency divider counter count is 314 (000100111010)2 . DB fast-lockup data The output voltage on pin DB provides an additional boost to charge the external lowpass filter capacitor for faster lockup times. One of 31 possible output voltage level signals is selected by bits 18 to 22. The DB level signal output occurs during 2 clock cycles when the reference frequency divider comparInput data format example ator signal FR is generated after OPR goes HIGH, or after LE goes LOW when data is written. The DB output subsequently becomes high impedance. Note that if bits 18 to 22 are all set to 0, this function is not activated and DB remains in the high impedance state. FIN input frequency divider = 10052, DB is high impedance: MSB 1 2 11 0 LSB 24 0 2 2 10 0 3 29 0 4 28 1 5 27 0 6 26 0 7 25 1 8 24 1 9 23 1 10 22 0 11 21 1 12 20 0 13 24 0 14 23 0 15 22 1 16 21 0 17 20 0 18 24 0 19 23 0 20 22 0 21 21 0 22 20 0 23 0 Main Counter (12bit : 32 to 4095) Control bits Swallow Counter (5bit : 0 to 31) DBpin Condition Select bits Figure 4. Swallow counter and main counter frequency divider data example NIPPON PRECISION CIRCUITS--6 SM5170AV Reference Frequency Divider (R-counter) Structure The reference frequency divider generates a comparator frequency signal (FR), which is input to the phase comparator, by dividing the reference oscillator frequency input either from an external signal on XIN or from a crystal oscillator connected between XIN and XOUT. The reference frequency divider is comprised of a fixed divide-by-4 prescaler and a 16-bit reference counter. A (= 4) B R=AxB=4xB A=4 B = 5 to 65535 R = 20 to 262140 Frequency settings Prescaler Reference counter Reference frequency divider ratio Counter set ranges Prescaler Reference counter Reference frequency divider ratio range Reference counter frequency data and LD setting The reference counter which determines the reference frequency divider ratio is set by bits 1 to 16. The lock detect signal output is set by bit 20. MSB 1 2 15 2 2 14 3 2 13 4 2 12 5 2 11 6 2 10 7 29 8 28 9 27 10 26 11 25 12 24 13 23 14 22 15 21 16 20 17 18 19 20 21 22 23 LSB 24 Reference Counter (16bit : 5 to 65535) LDpin Set bit Test bits (set to 00) Control bits Not used (set to 000) Figure 5. Reference counter data and LD output setting format Reference frequency divider example If the VCO output is (fVCO), the crystal oscillator frequency is 14.4 MHz and the channel bandwidth (fCH: comparator frequency (fR)) is 25 kHz, then the reference frequency divider ratio R is given by: Xtal Xtal 14.4 R = ---------- = ---------- = ------------ = 576 = 4 x 144 f CH fR 0.025 Therefore, the reference counter count is 144 (0000000010010000)2 . LD output The output on LD is set by bit 20. Bit 20 1 0 LD output Nor mal unlock signal output (normal operation) Unlock signal output OFF, LOW -level output Bits 15 to 19, bits 21 to 22 Bits 15 to 19 have no meaning, and should be set to 0. Bits 21 and 22 are factory test bits and should also be set to 0. NIPPON PRECISION CIRCUITS--7 SM5170AV Input data format example Reference frequency divider = 144, LD normal operation: MSB 1 2 15 0 LSB 24 1 2 2 14 0 3 2 13 0 4 2 12 0 5 2 11 0 6 2 10 0 7 29 0 8 28 0 9 27 1 10 26 0 11 25 0 12 24 1 13 23 0 14 22 0 15 21 0 16 20 0 17 0 18 0 19 0 20 1 21 0 22 0 23 0 Reference Counter (16bit : 5 to 65535) Not used (set to 000) LDpin Set bit Test bits (set to 00) Control bits Figure 6. Reference counter data and LD output setting example Standby Mode The SM5170AV enters standby mode when OPR goes LOW. In this mode, the states and functions shown in the table occur. Block DO and DB LD Phase comparator Input FIN Input XIN N counter R counter Latch data State Floating (high impedance) L O W -level output Reset Feedback resistor is cutoff (HIGH level) Feedback resistor is cutoff (HIGH level) Reset Reset Stored (while V D D 2 is within rating) In standby mode, some current flows into VDD1. Therefore, it is necessary to reduce VDD1 to 0 V to fully reduce current consumption and reduce power dissipation. Note that if both the VDD1 and VDD2 supplies are reduced to 0 V, the latch contents will be erased. In this case, VDD1 only should be reduced to 0 V. Standby mode is released when VDD1 rises and OPR goes HIGH. Phase Comparator Timing Diagram FR FV DO LD Figure 7. Phase comparator timing The DO output circuit polarity is configured for connection to an external passive filter. The signals compared are FV and FR, which are the internal FIN input frequency divider output signal and reference frequency divider output signal, respectively. NIPPON PRECISION CIRCUITS--8 SM5170AV INPUT/OUTPUT EQUIVALENT CIRCUITS XIN, XOUT DO From Internal Circuits Lagging Phase Correction Signal DO Leading Phase Correction Signal XIN To Internal Counter LD XOUT From Internal Circuits From Internal Circuits LD FIN From Internal Circuits DB From Internal Circuits DB From Internal Circuits FIN To Internal Counter From Internal Circuits From Internal Circuits From Internal Circuits OPR, CLK, DATA, LE TEST CLK DATA LE OPR To Internal Circuits TEST To Internal Circuits NIPPON PRECISION CIRCUITS--9 SM5170AV NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9808CE 1999.8 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS--10 |
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